Power semiconductor devices represented by power MOSFETs, such as power LDMOS mid power VDMOS, are widely used in power management systems. In order to reduce conduction losses and switching losses, power MOSFET is typically designed with low specific on-resistance and parasitic capacitance. With the rapid development of power semiconductor industry, the contradictory relationship between breakdown voltage and on-resistance has been relieved by reduced surface field (RESURF) technique and super junction concept. These technologies greatly reduce on-resistance at specific breakdown voltage to reduce the conduction losses induced by on-resistance. However, in the low-voltage and medium-voltage applications, the conduction losses of power semiconductor devices are no longer dominant. With the continuous increase in the operating frequency of power management systems, the switching losses caused by the switching process of the devices account for a higher proportion of the total power consumption. This increases the power consumption of the entire system and reduces its efficiency.
The conventional N-channel trench gate VDMOS, as shown in FIG. 1, whose gate structure extends through the P-body region and into the low-doped drift region so that it eliminates the JFET region resistance of conventional planar gate VDMOS. Furthermore, gate field plate can form a multi-sub accumulation layer of majority carriers in the drift region to reduce on-resistance at positive bias. However, the parasitic capacitance CGD caused by gate-drain overlap reduces switching speed and increases dynamic power consumption.
In order to reduce switching losses, a series of improved structures have been proposed to reduce the gate-drain parasitic capacitance CGD of the conventional trench gate VDMOS. As shown in FIG. 2, utilizing a thick oxide layer at the bottom of the trench gate effectively increases the distance between gate and drift region, and thus reducing the gale-drain parasitic capacitance CGD. For deep trench VDMOS devices, stepped gate electrodes and oxide layers can be used in deep trenches in order to reduce the gate-drain parasitic capacitance CGD, as shown in FIG. 3. B. J. Baliga proposed a deep trench VDMOS device based on a split gate structure in U.S. Pat. No. 5,998,833. The deep trench includes a control gate electrode isolated by dielectric and a separated gate electrode having the same potential as the source electrode. The separated electrode is used to shield the capacitive coupling effect between the control gate electrode and the drift region to reduce the gate-drain parasitic capacitance CGD. The structure is shown in FIG. 4; the deep trench VDMOS structure proposed by J. Zeng in U.S. Pat. No. 6,683,346 also applies the same principle, a dielectric layer is used to isolate the channel region control gate from the gate structure at the end of the trench gate to reduce the gate-drain parasitic capacitance CGD.
FIG. 21 shows a cross-sectional schematic view of the conventional N-channel planar gate LDMOS, whose gate electrode extends to drain side and covers a portion of the shallow trench isolation (STI) located in the drift region to form a gate field plate. The gate field plate improves breakdown voltage by adjusting device surface electric field. Meanwhile, the gate field plate forms a multi-sub accumulation layer of majority carriers on the surface of the drift region to further reduce on-resistance. However, the longer gate field plate also increases the overlap between gate and drift region, which leads to a larger gate-drain parasitic capacitance CGD, thereby increasing device twitching time and dynamic power consumption.
To achieve lower gate-drain parasitic capacitance CGD of the conventional N-channel planar gate LDMOS. Vishnu Kbemka et. al proposed a split gate structure based on lateral power devices in U.S. Pat. No. 8,969,958, as shown in FIG. 22. This structure forms a control gate and a split gate whose potential is equal to source electrode, by separating the gate field plate of the conventional LDMOS device. The split gate structure reduces gate-drain overlap, and shields the capacitive coupling effect between control gate electrode and drift region, thereby significantly reducing the gate-drain parasitic capacitance CGD and improving the switching performance but without the influence of device's breakdown voltage.
Prior art method of reducing gate-drain parasitic capacitance CGD is typically focusing on optimizing the gate structure except for the control gate to reduce the dynamic power consumption. However, the charging and discharging process of the parasitic gale-source and gate-drain capacitance near the channel region of the power MOSFET device still have great impact on device switching characteristic. Therefore, there is still plenty of room for optimization and improvement in source end structure near the channel region, so as to further improve the switching speed and reduce the dynamic power consumption of device.